As device sizes approach dimensions in the 100 nm range, numerous problems occur in achieving functionality that are not present in ULSI and VLSI integrated circuits manufactured today. For logic, these include sub-threshold effects, output conductance, and power gain of the device. For memory, volatile such as dynamic random access memories (DRAM) and non-volatile such as electrically erasable programmable random access memories (E.sup.2 PROM), these include sub-threshold conduction which leads to leakage of the stored charge or the loss of the clearly defined threshold. To improve performance and the functionality per unit area, alternatives are needed to the conventional path of scaled designs and technology improvements.
Coulomb blockade is now a conceptually well-understood subject such as described in a publication by H. Matsuoak et al., entitled "Coulomb blockade in the inversion layer of a Si metal-oxide-semiconductor field-effect transistor with a dual gate structure," Appl. Phys. Lett. 64, 586 (1994)
Coulomb blockade is also discussed in a publication by E. H. Nicollian and R. Tsu, entitled "Electrical properties of a silicon quantum dot diode," J. Appl. Phys., 74, 4020 (1993).
A few attempts have been made at making memory structures utilizing Coulomb blockade such as in the publications by K. Yano et al., entitled "A room-temperature single-electron memory device using a fine-grain polycrystalline silicon," Dig. of Int. Electron Dev. Mtg., Dec. 1993, Washington D.C., p. 541 and K. Bock et al., entitled "Proposal for the concept of ultradense integrated memories based on Coulomb blockade at room temperature," Electron. Lett., 29, 2228, (1993).
All the above examples and attempts, however, utilize the conductance effects on in-path conduction of Coulomb blockade.
In a publication by K. K. Likharev et al. entitled "Single Electronics" Scientific American June 1992, pp. 80-85, single-electron tunneling (SET) oscillations through a tunnel junction is described. At page 85, column 1, it recites "In circuits based on single electronics, bits of information can be represented as the presence or absence of individual electrons."
In U.S. Pat. No. 5,055,890 which issued on Oct. 8, 1991 to L. R. Dawson et al., a nonvolatile three dimensional memory is described having a storage channel which stores charge carriers. Charge carriers flow laterally through the storage channel from a source to a drain. The charge may be confined in a compound semiconductor such as GaAs or InAs by a quantum well formed by the different energy band gaps of adjacent layers of for example AlAs or AlSb.
In U.S. Pat. No. 5,347,140 which issued on Sep. 13, 1994 to Y. Hirai et al., an electron transfer device is described which uses alternately disposed quantum dot structures and quantum wire structures and a plurality of electrodes for controlling internal potentials of respective quantum wires and dots and wherein one of the quantum wires and one of the quantum dots adjacent to each other are connected via a potential barrier capable of exhibiting a tunnel effect there between.